As semiconductor memory processing technology has advanced, smaller and smaller semiconductor memory devices are being introduced. Deep sub-micron processes are now being developed to facilitate production of small, highly integrated, memory devices. In order to improve the performance of transistors developed using deep sub-micron technology, the threshold voltage (Vth) of the transistor may be reduced. When the threshold voltage is lowered, however, both the saturation current of the transistor in its “on” state and the leakage or “off-current” (Ioff) of the transistor in its “off” state may increase.
FIG. 1 is a diagram of a memory cell array 100 that may be used to illustrate the impact of a leakage current. The memory cell array includes a plurality of memory cells 102, 104, 106, . . . . As will be appreciated by those of skill in the art, these individual memory cells 102, 104, 106 are typically arranged in rows and columns to form the memory cell array 100. As shown in FIG. 1, in the memory cell array 100, the memory cells 102, 104, 106, . . . are located at intersections of a plurality of word lines (WL0, WL1, WL2, . . . ), a bit line (BL) and a complementary bit line (BLB). For convenience of explanation, in the following description it is assumed that the power supply voltage (VDD) corresponding to logic level “1” is stored in a first node (NA) and the ground or reference voltage (VSS) corresponding to logic level “0” is stored in a second node (NB). In the example of FIG. 1, the ground voltage (VSS) is set as 0 volts, although other ground voltages (VSS) may be used.
When the first word line (WL0) is enabled, the first memory cell 102 is activated and data stored in the first memory cell 102 is transferred to the bit line (BL) and the complementary bit line (BLB). Data in the first memory cell 102 experiences charge sharing such that a voltage difference between the bit line (BL) and the complementary bit line (BLB) occurs. Referring to FIG. 1, the bit line (BL) moves toward the power supply voltage (VDD) level and the complementary bit line (BLB) moves toward the ground voltage (VSS) level such that a voltage difference occurs. This voltage difference is sensed and amplified by a sense amplifier (not shown) so that the data in the memory cell 102 can be determined.
As shown in FIG. 1, both memory cell 104, which is connected to the second word line (WL1), and memory cell 106, which is connected to the third word line (WL2), are deactivated such that they are not connected to the bit line (BL) or the complementary bit line (BLB). However, the off-current (Ioff) or leakage current of the memory cells 104 and 106 flows from the bit line (BL) into the transistors of memory cells 104 and 106 storing logic zeros such that the power supply voltage level of the bit line (BL) is lowered. As a result, the voltage difference between the bit line (BL) and the complementary bit line (BLB) decreases. This decrease results in a reduction of the sensing speed of the sense amplifier.
When the word lines (WL0, WL1, WL2, . . . ) are enabled in response to a decoded row address, the bit line (BL) and the complementary bit line (BLB) are precharged to the power supply voltage (VDD) in response to a precharge signal (PRE). After the bit line (BL) and the complimentary bit line (BLB) are precharged a voltage difference due to the memory cell data occurs that is sensed and amplified by the sense amplifier. Circuit blocks related to these operations are shown in FIG. 2.
As shown in FIG. 2, the circuit blocks include a memory cell array block 100, a row decoder 210, a pre-address decoding circuit and control signal generation unit 220, a bit line precharge unit 230 and a sense amplifier 240. The row decoder 210 and the pre-address decoding circuit 220 perform operations for enabling word lines (WL0, . . . , WLn), and the bit line precharge circuit 230 that responds to a precharge signal (PRE) performs operations to precharge the bit line (BL) and the complementary bit line (BLB) to the power supply voltage (VDD) level. The sense amplifier 240 senses and amplifies the bit line (BL) and the complementary bit line (BLB) in which a voltage difference occurs in response to a control signal (SENSE).
FIG. 3 is a diagram illustrating the operational timing of the circuit of FIG. 2. Referring to FIG. 3, intervals (a) through (d) are shown. In interval (a), the precharge signal (PRE) is at a “low” logic level and in response to this the bit line (BL) and the complementary bit line (BLB) are precharged to the power supply voltage (VDD) level. Interval (b) is a floating interval during which the precharge signal (PRE) transitions to a “high” logic level (i.e., is disabled). In interval (c), word line (WL0) transitions to a “high” logic level and is enabled. During interval (c) a voltage difference between the bit line (BL) and the complementary bit line (BLB) also occurs (due to the memory cell data), and a control signal (SENSE) transitions to a “high” logic level (i.e., is enabled). As a result, the voltage difference between the bit line (BL) and the complementary bit line (BLB) is sensed and amplified. In interval (d), the precharge signal (PRE) transitions to a “low” logic level (i.e., is enabled) such that the bit line (BL) and the complementary bit line (BLB) are again precharged to the power supply voltage (VDD) level.
In the operation of the circuit of FIG. 2, during interval (b), before the word line (WL0) is enabled, the voltage levels of the bit line (BL) and the complementary bit line (BLB), which are precharged to the power supply voltage (VDD) level, are lowered due to the effect of the off-current (Ioff) described above with respect to FIG. 1. Accordingly, additional time may be required to arrive at the voltage difference between the bit line (BL) and the complementary bit line (BLB) that can be sensed by the sense amplifier. Thus, the off-current can act to reduce the operation speed of the memory device.